High-Speed Digital Design and PCB Layout Including IoTand 5G
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The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as a lack of control over impedance and reflections, crosstalk and bypassing failings, time delays, false triggering and reflections; failure to meet EMI and EMC requirements. It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency,
This three-day course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity. This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB. Persons who would benefit from the course include digital logic engineers, system architects, technicians, PCB layout professionals, IC designers, IC package designers, application engineers, anyone who works with high-speed digital logic, anyone who works with any logic implemented in the submicron processes that are becoming standard in the industry, engineering managers, and project managers.
Students will receive a comprehensive set of course notes by the instructor. The 26-page booklet “How to Become a Circuit Master” assembled and authored by the instructor will be included along with a 29-page supplement is included which provides backup info for various concepts developed in the course.
What You Will Learn:
- Basic fundamentals regarding the interaction of velocity, PCB material, capacitance, inductance, and characteristic impedance (Zo).
- Rise and fall times of logic families, how to use an oscilloscope to measure ISI, jitter, eye diagrams, skin effect, SSO, SSN, and tan loss.
- How to design a transmission line for Zo, proper termination for minimizing reflections, and how to layout a PCB-microstrip, stripline and differentials.
- How to provide bypassing between power and ground and power delivery to the high-speed IC switching logic.
- How to minimize crosstalk, via discontinuity and match cables/connectors for high-speed signal transmission.
- How to control high speed clock and properly layout the bus structures (LVDS, multidrop, etc.)
- All the details for laying out differential signaling for impedance control, minimizing reflections, and controlling EMI.
Frequency, Time, and Distance; Lumped Versus Distributed Systems; EM Fields; Geometry, C, L, and Zo; interrelationships and C & L Resonance. High-Speed Properties of Logic Gates Quiescent vs Active Dissipation; Driving Capacitive Loads; Input Power and External Power; TTL, CMOS, SiGe, In Pn, ECL and GaAs; Output power, speed and engineering disciplines, Dv, di effects and Voltage Margins; Low K Di-electrics, ISI, SSO, SSN, eye diagram and ground bounce.
- Measurement Techniques
Rise Time and Bandwidth of Oscilloscopes and probes; Viewing a Serial Data Transmission System, the eye pattern closure ISI, Skin effect, tan loss and PLL and DLLs.
- Transmission Lines
Effects of Source and Load Impedance; Special Transmission Line Cases; Determining Line Impedance & Propagation Delay Using TDR; Skin/proximity effect and dielectric loss; Defining S Parameters and how to use them and the capacitive Load – Zo and propagation delay; Matching Zo with trace alterations (neckdowns) – minimizing the C load; 900, 450 bends – are they concerns; Characteristics impedance and propagation delay for all Transmission Line configurations.
End/Source/Middle Terminators; AC Biasing for End Terminators, where should it be used and how to choose the capacitor; Hairball networks, bifurcated lines and capacitive stubs; terminating differentials – eliminating common mode and minimizing power. What causes differentials unbalance? Diode and active terminators, Resistor Selection and Crosstalk in Terminators.
Capacitance and Inductance of Vias; return current and its relation to vias, through hole, blind, buried, microvias; intelligent vias and autorouters, vis discontinuity and via resonance concerns. Ground Planes & Layer Stacking
- High-Speed Current follows the path of least inductance;
Crosstalk in solid and slotted ground planes; inductive/capacitive ratios for microstrips, striplines, and asymmetric, dual, and edge LVDS. Guard Traces – do they stop crosstalk? Can they resonate? Near-End and Far- End Crosstalk; separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge and split planes – CMOS/TTL, PECL and analog using the same bias voltages. How to stack Printed Circuit Board layers (e.g., 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal layers, minimizing warpage; Interplane Capactiance – How thin, what material and stackup placement.
- Power Systems
Providing a stable Voltage Reference – Cu planes; Distributing Uniform Voltage – sense lines, bulk C and interplane C and choosing a bypass capacitor – electrolytic/tantalum and ceramic. Power plane resonance – serial and parallel, how to minimize both; designing a .1 ohm bypass system up to Fknee and designing for constant ESR; IC die capacitance, discrete C in the IC package and Why the 0201 – both for better bypassing and EMI control. Minimizing the inductance/capacitance layouts for SOICs, PLCCs, and various configurations of BGAs.
- Connectors & Cables
Mutual and Series Inductance – how connectors create crosstalk and EMI and using connectors on a multidrop bus (Z mismatch reflection) and how to match Zc to Zo. Measuring coupling in a connector, continuity of ground underneath a connector and special connectors for high-speed requirements – crosstalk and matching Zo. Differential Signaling through a connector.
Multidrop systems: drivers and transceivers; how they function, clock rates, typical failures. ISI – Minimize the effect with Equalization and Pre-emphasis using CTLE and DFE techniques. LVDS: types, unbalance, noise, layout and making them function and methods to speed up busses – distributing driving and load capacitance matching.
- Clock Distribution
Timing Margin and Clock Skew; using low-impedance drivers and clock distribution lines and controlling crosstalk on clock lines. Delay adjustments – serpentine traces and controlling clock signal duty cycle using the integrator.
- Differential Signaling
Attributes/drawbacks of loosely/tightly coupled differential pairs; definition and examples of differential and common modes V and I; differential impedance: odd and even modes. Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials. Reflections and crosstalk in differentials; metastability, clock skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram; and matching electrical lengths.
- Internet of Things (IOT) and 5G Transmission
How to design a cabling/connector layout to minimize crosstalk and attenuation on Signal lines of various CLK frequencies and edge rates. How to minimize radiation and susceptibility and suppress other EMI effects. How to shield cables and design a grounding system. How to interface to a DDR memory architecture. Controlling 5G signals at 24 GHz to 54 GHz. Designing a PAM4 transmission, how to control skew on differential drivers. Why mechanically spread glass in the PCB is essential. Equalization Techniques, CTLE and DFE to capture the data and minimize data skew and enhance the eye diagram. A 27GHz channel will be designed in class using the above techniques.
Robert Hanson, MSEE has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing Commercial Airline products, Mr. Hanson has worked with non-EEs and EE’s. His over 40 years of work experience in the design, manufacturing, and testing areas has enabled him to consult and train both nationally and internationally. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and LoraL, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military). His teaching experiences include electronic conventions, over 100 private companies on site, and universities. Boeing Company awarded him Aerospace Man of the Year for saving $6,000,000 for inventing a new testing technique for the Boeing B-1 bomber electronics.
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